1. Field of the Invention
This invention relates generally to an analog-to-digital converter for converting an analog signal into a digital signal, and more particularly to method and apparatus for analog-to-digital conversion by utilization of charging and discharging actions of a capacitor.
2. Description of the Prior Art
In a typical analog-to-digital converter, a capacitor is electrically charged by an input signal until a value of an output voltage thereof reaches a specified one corresponding to the input signal, and thereafter the capacitor is caused to discharge until the value of the output voltage thereof decreases to a predetermined one. The time it takes for the value of the output voltage to change from the specified one to the determined one is measured by counting clock pulses or by other means, and this time is digitized. One of such conventional analog-to-digital converters is shown in FIG. 1, in which a reference voltage VR is applied to an input terminal 1a of a multiplexer 1. To other input terminals P1 through P4 is applied an analog voltage of an analog signal from a sensor for detecting a physical quantity or the like. An output terminal Q1 of the multiplexer 1 is connected to the negative pole of a battery cell 2, of which positive pole is connected to a noninverting input terminal of a comparator 5 by way of a buffer gate 3 and a switch 4. The noninverting input terminal of the comparator 5 is grounded through a constant current source 6, and is also grounded through the capacitor 7. An inverting input terminal of the comparator 5 is connected to the positive pole of a battery cell 8 for applying a reference voltage. A decoder 9 receives a channel selection signal through lines 10, and transmits the decoder signal to the multiplexer 1 through a bus line 11. The analog voltage applied to the input terminals P1 to P4 of the multiplexer 1 is successively sent out from the output terminal Q1 of the multiplexer 1 by the channel selection signal sent out in the lines 10 from a processing circuit 15. The analog voltage sent out from the output terminal Q1 is synthesized with a voltage VBE1 for permitting this analog voltage of any one of 0 V into a digital signal, and the capacitor 7 is charged during the low level period of a start signal for starting the analog-to-digital converting operation from the processing circuit 15. While the start signal is at a low level, the switch 4 is closed.
After completion of charging the capacitor 7, the processing circuit 15 raises the level of the start signal to be high and the switch 4 is opened, so that the capacitor 7 is discharged with a constant current IR. The voltage of the capacitor 7 is compared with a voltage VBE2 applied to the inverting input terminal by the comparator 5, of which output terminal converts an analog voltage into a digital voltage and transmits a stop signal to show that the conversion is over.
FIG. 2 is a timing chart of start signal and stop signal in FIG. 1. When a start signal 21 shown in diagram (1) of FIG. 2 descends to a low level, the voltage of the capacitor 7 begins to rise as indicated by line 22 in diagram (2) corresponding to the magnitude of input analog voltage Vin and bias voltage VBE1 and reaches a specified value (=Vin+VBE1). When this capacitor voltage reaches VBE2, a stop signal 23 rises to a high level as shown in diagram (3). When the start signal 21 returns to the high level, the switch 4 is opened, and the voltage of the capacitor 7 declines, and when the voltage thereof dropping below voltage VBE2, the stop signal 23 turns from the high level to a low level.
Measuring the time Tx from the rise of start signal 21 to the fall of stop signal 23, the input voltage Vin which is an analog voltage applied to the input terminals P1 to P4 of the multiplexer 1 may be calculated in the following equation. EQU (Vin+VBE1-VBE2).times.C=IR.times.Tx (1)
Where C is the capacity of capacitor 7. Changing the input voltage Vin to a reference voltage VR and leading out to output terminal Q1 yields Eq. (2). EQU (VR+VBE1-VBE2).times.C=IR.times.TR (2)
Where TR is the time from rise of start signal 21 to fall of stop signal 23.
Eq. (3) is established when VR is 0 volt (VBE1-VBE2). EQU (VBE1-VBE2).times.C=IR.times.TO (3)
Where TO is the time from rise of start signal 21 till fall of stop signal 23 when VR is 0 volt. From Eqs. (1) to (3), Eq. (4) is obtained. ##EQU1## Where VR, Tr, and TO are predetermined values. Therefore, when the time Tx is measured, the digital value of the input voltage Vin may be calculated from Eq. (4).
FIG. 3 is a graph showing the relation between said input voltage Vin and a voltage Vc of the capacitor 7. The line indicated by number 31 expresses Eq. (5). EQU Vc=Vin+VBE1 (5)
At point 32 on line 31, the voltage Vc is at the level of voltage VBE2, and when the charging voltage Vc of capacitor 7 is above the reference voltage VBE2, an analog-to-digital conversion is possible, but when the input voltage Vin between the sensor and processing circuit becomes less than (VBE2-VBE1) (a negative voltage) due to the effect of noise or fluctuation of earth voltage, the charging voltage Vc becomes less than the voltage VBE2 and a stop signal is not generated, so that a fall waveform is not given to the processing circuit 15 by the comparator 5. The processing circuit 15 is adapted in such a manner as to operate the input voltage Vin based on Eq. (4) depending on the fall waveform from the comparator 5, and to change over the channel to transmit the next input signal to the output terminal Q1 through the multiplexer 1. Therefore, when fall waveform is not obtained from the comparator 5, the processing circuit 15 cannot proceed to a subsequent processing. That is, while the input voltage Vin is less than (VBE2-VBE1), even if a start signal is issued as shown in FIG. 4(1), the voltage Vc is less than VBE2 as demonstrated in FIG. 4(2), and the stop signal 23 remains at the low level as in FIG. 4(3), so that the processing circuit 15 cannot move to a subsequent processing.